Second Amendment And Restated of "S" Process Development Agreement

Exhibit 10.1


Confidential Treatment Requested

under 17 C.F.R. a7a7 200.80(b)94),

200.83 and 240.24-b-2

Second Amendment and Restatement of

" S" PROCESS DEVELOPMENT AGREEMENT (effective as of December 28, 2002)

between


INTERNATIONAL BUSINESS MACHINES CORP.


And


ADVANCED MICRO DEVICES, INC.


Confidential treatment has been requested for portions of this exhibit. The copy filed herewith omits the information subject to the confidentiality request. Omissions are designated as *** . A complete version of this exhibit has been filed separately with the Securities and Exchange Commission.

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 1 of 87


EXECUTION VERSION


This Agreement is made effective as of the 28th day of December, 2002 (hereinafter referred to as the " Effective Date" ) by and between International Business Machines Corporation (" IBM" ), incorporated under the laws of the State of New York, U.S.A. and having an office for the transaction of business at 2070 Route 52, Hopewell Junction, NY 12533, U.S.A, and Advanced Micro Devices having an office for the transaction of business at One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 " (AMD)" . IBM and AMD may be individually referred to herein as a " Party," or collectively as the " Parties."


WHEREAS , IBM has been developing leading edge semiconductor manufacturing processes with Sony and Toshiba, and the Parties hereto desire to continue to participate in development efforts under this Agreement;

WHEREAS , the Parties possess complementary skills and know-how, which the Parties wish to contribute toward such process development;


WHEREAS , each Party agrees to provide certain personnel and grant the other Parties certain technology licenses in support of such process development;

WHEREAS , through the use of such complementary skills and know-how the Parties desire to achieve resource efficiencies and cost savings, and reduce the technical risk associated with the development of high end semiconductor processes in order to complete development of and put into production, leading edge high end semiconductor manufacturing processes sooner than would be possible with any of the Parties acting independently;


NOW THEREFORE , in consideration of the premises and mutual covenants contained herein, as well as for other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties agree as follows. For avoidance of doubt, the Agreement as defined below covers its subject matter after its Effective Date including matters provided for in the " S" Process Development Agreement (Effective as of December 28, 2002) as amended and restated on September 15, 2004 and as set forth herein.


SECTION 1 - DEFINITIONS

Unless expressly defined and used with an initial capital letter in this Agreement, words shall have their normally accepted meanings. The headings contained in this Agreement or in any exhibit, attachment or appendix hereto are for reference purposes only and shall not affect in any way the meaning or interpretation of this Agreement. The word " shall" is mandatory, the word " may" is permissive, the word " or" is not exclusive, the words " includes" and " including" are not limiting, and the singular includes the plural. The following terms shall have the described meanings:

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 2 of 87

" Agreement" means the terms and conditions of this Second Amendment and Restatement of " S" Process Development Agreement together with any exhibits, attachments and appendices hereto.


" AMD Bump Project Leader" means the individual, if any, appointed by AMD pursuant to Section 4.4 below.

" AMD Project Leader" means the individual, if any, appointed by AMD pursuant to Section 4.5 below.

" AMD FMV" means a single AMD flash memory venture at any point in time, in which AMD has an ownership interest representing a right to participate in making decisions for such flash memory venture (i.e. a shareholder' s right to vote), which is the lesser of (i) *** percent ( *** %) or (ii) the largest single owner, but not less than *** percent ( *** %) of such flash memory venture, and which produces flash memory products, provided, that such entity shall be considered an AMD FMV only so long as such ownership exists.

" AMD High Performance Integrated Circuit" means an Integrated Circuit manufactured using an AMD High Performance Process.


" AMD High Performance Process" means any 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process which incorporates portions of High Performance Device Information, which AMD uses exclusively to produce the highest performing *** percent ( *** %) of wafers manufactured in the applicable technology generation (e.g. 32nm, 22nm) in any given quarter. Performance will be determined by AMD' s AC and DC transistor performance data, wherein any disputes will be resolved by the Management Committee.


" AMD Non-High Performance Integrated Circuit" means an Integrated Circuit manufactured using an AMD Non-High Performance Process.


" AMD Non-High Performance Process" means AMD' s 32nm, 22nm or subsequent node CMOS semiconductor manufacturing processes used by AMD to manufacture Semiconductor Products other than AMD High Performance Integrated Circuits.


" AMD Pre-T0 Project Leader" means the individual, if any, appointed by AMD pursuant to Section 4.3 below.


" AMD Pre-T0 Steering Committee Member" means the individual appointed by AMD pursuant to Section 4.2 below, to provide technical guidance to the Management Committee for the Pre-T0 Activities.


" ASIC Product" shall mean an SOI Integrated Circuit or AMD High Performance Integrated Circuit that is not a Foundry Product and wherein all of the following conditions are met: (i) at least one of (a) the functional requirements, or (b) the design, for such SOI Integrated Circuit or

*** Confidential Treatment Requested

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 3 of 87

AMD High Performance Integrated Circuit product is provided to a Party from a Third Party; (ii) such Party participated in an aspect of the definition and design of such product; and (iii) such Party is contractually bound to manufacture such product solely for, and to sell such product solely to, such Third Party or its distributor or other recipient solely for the benefit of such Third Party, provided that ASIC products shall not include SOI Integrated Circuits or AMD High Performance Integrated Circuits in which the Party modifies its product designs to add or modify a feature or function required by the Third Party, such modifications comprising a change of less than *** percent ( *** %) of the logical functions of the product, even if said product design is only made available to the Third Party.

" Background Know-How" means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the performance of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3. Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist Technology, Memory, SiGe Technology, Chip Designs or Post-Silicon Devices.

" BEOL" (Back End of Line) shall mean those aspects of Background Know-How and Specific Results that are directed to methods and processes of interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a dielectric, up to and including polyimide passivation and final via formation but not including Bump Technology and Packaging Technology. For the avoidance of doubt, " BEOL" shall not include local interconnects made of tungsten.

" Bulk CMOS" means 90nm, 65nm and 45nm CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.

" Bulk CMOS Information" means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii) selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4.

" Bump Technology" means the technology associated with connecting an Integrated Circuit to a chip carrier including IBM' s collapsible chip carrier connection (" C4" ) interconnect technology as further defined in Exhibit A that is developed during the term if this Agreement for use with, but not limited to, the semiconductor process technologies also developed under this Agreement. Bump Technology shall include the following process steps: bump limiting metallurgy deposition, photolithography, solder deposition, etching, solder reflow and cleaning, and non-solder interconnect technology.

" ***" shall mean *** and its subsidiaries located in *** .

" *** -AMD Manufacturing Facility" shall mean any facility for the manufacture of Integrated Circuits located in *** or Dresden, Germany and either owned entirely by *** and AMD or owned by *** , AMD and all of the remaining such ownership interest is solely owned or

*** Confidential Treatment Requested

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 4 of 87

controlled, directly or indirectly, by a government entity or one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development, manufacture, marketing or sale of Semiconductor Products.


" Chip Design(s)" means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that " Chip Designs" shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.

" CMOS 10S" means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.1, attached hereto.


" CMOS 10SE" means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 10S, as further defined in Exhibit A.2.


" CMOS 11S" means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.3.


" CMOS 11S2" means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 11S, as further defined in Exhibit A.4.

" CMOS 12S" means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.5.


" CMOS 12S2" means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 12S, as further defined in Exhibit A.6.

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 5 of 87

" CMOS 13S" means a 32 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.7.

" CMOS 13S2" means a 32 nanometer CMOS logic fabrication process, which is a performance enhanced version of CMOS13S, and which is researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.8.

" CMOS 14S" means a 22 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.9.


" Designated Invention" means an Invention for which a patent application has been filed by one or more of the Parties pursuant to Sections 11.1 or 11.2.


" Derivative Process(es)" shall have the meaning ascribed to it in Section 8.1

" Development Facilities" means the (i) IBM Development Facilities and (ii) any other facilities agreed to by the Parties in writing.


" Embedded DRAM" or " eDRAM" means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).


" Foundry Company(ies)" means an entity having a majority of its revenue arising from the sale of Integrated Circuits wherein all the following conditions are met: (i) the *** , or *** and/or *** , for such Integrated Circuit product are *** ; (ii) *** ; and (iii) *** is contractually bound to *** . Foundry Company also includes any other entity that has as its *** , wherein at least *** percent ( *** %) of the ownership interest in such entity is held by a *** (as defined in the first sentence of this paragraph), and wherein such *** .


" Foundry Product" shall mean an Integrated Circuit wherein all the following conditions are met: (i) the *** , or *** and/or *** , for such Integrated Circuit product *** ; (ii) *** of such product (except for providing standard design libraries, design enablement tools or other intellectual property to the Third Party to specifically assist with the design of the product); and (iii) *** is contractually bound to *** .

" High Performance Device Information" means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on substrates, not including *** or *** .

*** Confidential Treatment Requested

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 6 of 87

" High Performance Integrated Circuit" means an Integrated Circuit manufactured in a 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process using High Performance Device Information.


" High Sensitivity Pre-T0 Information" shall have the meaning ascribed to it in Section 8.18.

" IBM Bump Technology Project Leader" means the individual appointed by IBM pursuant to section 4.4 below.

" IBM Development Facilities" means the (i) IBM 200mm or 300mm wafer process development facility used for conducting the Process Development Projects; (ii) the IBM Thomas J. Watson Research Center: and (iii) any other IBM facilities agreed to by the Parties in writing.

" IBM Pre-T0 Activities" means the activities conducted by IBM on the CMOS 13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility by IBM prior to the Commencement Date.

" IBM Pre-T0 Information" means all information and items developed or acquired by IBM pursuant to the IBM Pre-T0 Activities and delivered by IBM, in its sole discretion, to the Pre-T0 Activities.


" IBM Pre-T0 Project Leader" means the individual appointed by IBM pursuant to Section 4.3, below, to provide day-to-day oversight for the Pre-T0 Activities.

" IBM Project Leader" means the individual appointed by IBM pursuant to Section 4.5, below, to provide day-to-day oversight for the Process Development Projects.


" IBM Pre-T0 Steering Committee Member" means the individual appointed by IBM pursuant to Section 4.2, below, to provide technical guidance to the Management Committee for the Pre-T0 Activities.

" Industry Standard CMOS" means a 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process for high volume foundry manufacturing of Semiconductor Products ( *** ) whose price and performance characteristics are similar to *** .


" Industry Standard Information" means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, or (ii) applicable to Industry Standard CMOS and selected by IBM either for incorporation into an IBM Industry Standard CMOS process or otherwise selected pursuant to Section 3.4.

*** Confidential Treatment Requested

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 7 of 87

" Integrated Circuit" means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, " Integrated Circuit" shall include charge-coupled devices (" CCDs" ).


" Invention" means any invention, discovery, design or improvement, conceived or first actually reduced to practice solely or jointly by one or more Representatives of one or more of the Parties or their respective contractors during the term of this Agreement and in the performance of the Process Development Projects.

" Licensed Product" means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information, SOI Device Information, or any combination thereof, other than Foundry Products.

" Lithography" shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.

" Management Committee" shall have the meaning ascribed to it in Section 4.1.


" Mask Fabrication and Photoresist Technology" shall mean any process, procedure, Proprietary Tools (e.g. the Niagara software developed by IBM), or hardware tool used in the fabrication of photomasks, as well as the photomasks themselves, and/or the formulation and/or manufacture of photoresist; provided, however, that " Mask Fabrication and Photoresist Technology" shall not include Lithography or the evaluation of photomasks or photoresists for use in the technologies developed and researched hereunder.

" Memory" means Chip Designs and fabrication processes specifically related to read only memory (ROM), dynamic random access memory (DRAM), programmable ROMs, magnetic RAM (MRAM), ferroelectric RAM, and Embedded DRAM. For the avoidance of doubt, " Memory" shall not include static RAM (SRAM) macros utilized in the Process Development Projects as test vehicles.


" Net Selling Price" for each unit of a particular ASIC Product or wafers (only pursuant to Section 5.7) means the net revenue recorded by AMD (including Wholly Owned Subsidiaries and Related Subsidiaries of AMD) with respect to an ASIC Product or such wafers (only pursuant to Section 5.7) less (a) shipping, (b) insurance, and (c) sales, value added, use or excise taxes, to the extent to which they are actually paid or allowed, and less allowances to the extent they are actually allowed. If ASIC Products or such wafers (only pursuant to Section 5.7) are

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 8 of 87

sold, leased or otherwise transferred in a higher level of assembly or in the course of a transaction that includes other products or services with no separate bona fide price to be charged for the ASIC Products, the applicable Net Selling Price for the purpose of calculating royalties shall be the fair market value of the ASIC Product or such wafers (only pursuant to Section 5.7), but no less than the average Net Selling Price of all such units of other ASIC Products or such wafers (only pursuant to Section 5.7) sold, leased, or otherwise transferred to a Third Party by AMD (and/or by Wholly Owned Subsidiaries and Related Subsidiaries of AMD), whichever the case may be, during the preceding half year.


" Packaging Technology" means any process, procedure, software, or hardware tools used in the packaging of integrated circuit products into single-chip packages, multi-chip packages, or any other higher levels of assembly,; provided, however " Packaging Technology" shall not include the formation of layers on a wafer up to and including the final via layer (referred to as LV, TV, or FV level) and shall not include Bump Technology, but shall include any process, procedure, or practice subsequent to any such steps included in Bump Technology.


" Post-Silicon Devices" means transistors on substrates other than silicon or transistors with critical dimensions less than *** nm which are not *** or *** , unless otherwise set forth in this Agreement (e.g. Exhibit A.10, which may be updated from time to time by the Parties).


" Pre-T0 Activities" means the IBM Pre-T0 Activities and the activities conducted on the CMOS 13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility under this Agreement pursuant to the technical objectives, and the Pre-T0 In-Scope Technical Subjects, as further defined in Exhibit A and the schedule set forth in Exhibit B.


" Pre-T0 Exit" means the point in time where development work begins on the Process Development Project. At this point in the program the Management Committee has determined the Strategic Technology Objectives, Technology Implementation Options and the T-Bulk, T1 and T2 dates for the applicable technology.


" Pre-T0 In-Scope Technical Subjects" means the subjects listed in Exhibit A.10, as updated from time to time by agreement of the Management Committee.


" Pre-T0 Information" means the IBM Pre-T0 Information and all information and items developed or acquired pursuant to the Pre-T0 Activities.


" Pre-T0 Steering Committee" shall have the meaning ascribed in Section 4.2.

" Process Development Project(s)" means the CMOS 10S, CMOS 10SE, CMOS 11S, CMOS 11S2, CMOS 12S, CMOS 12S2, CMOS 13S , CMOS 13S2 and if its development is continued pursuant to this Agreement, CMOS14S, development work and any Bump Technology development work conducted jointly by Representatives of the Parties pursuant to the terms and conditions of this Agreement, as more fully set forth in Section 3.1, below.

*** Confidential Treatment Requested

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 9 of 87

" Project Leaders" means the IBM Project Leader and the AMD Project Leader.

" Proprietary Tools" means software (in source code form or in object code form), models and/or data, and other instrumentalities that are not commercially available and are either owned by a Party or under which a Party has the right to grant royalty-free licenses, and that are used in Process Development Projects.


" Qualification" means the T2 date identified in the schedule for each Process Development Project, as set forth in Exhibit B.


" Related Subsidiary" shall mean a corporation, company or other entity:

(a) one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto; or

(b) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity one hundred percent (100%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto;

provided that in either case, such entity shall be considered a Related Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to the Related Subsidiary, only so long as such ownership or control exists.


" Representative(s)" means, a Party' s employees and employees of a Party' s Wholly Owned Subsidiaries.

" Semiconductor Product" means a component that contains an Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors).


" Server" means an electronic device performing information processing functions that primarily provides shared applications, resources, information, or services to other systems or collections of systems or multiple end-users/clients through an internal or external communications connection or network, or through the Internet and is designed to support either AIX or another UNIX operating system.

Second Amendment and Restatement of " S" Process Development Agreement between AMD and IBM IBM - AMD Confidential Page 10 of 87

" Silicon-Germanium Technology" or " SiGe Technology" means semiconductor fabrication processes and design techniques incorporating silicon and germanium layers, including those processes and design techniques for use in HEMTs, photodetectors, HBTs or any other applications of bipolar transistors, provided, however, " SiGe Technology" shall not include strained silicon channel MOSFET or any mobility enhancement techniques for FETs techniques carried out on SOI Wafers or High Performance Integrated Circuit wafers. Furthermore, " SiGe Technology" shall not include material and device learning out of " SiGe Technology" that is applicable to the items outlined in Exhibit A.10 of this Agreement under the " FEOL" section of Pre-T0 In-Scope Technical Subjects.

" Silicon-On-Insulator Wafer" or " SOI Wafer" shall mean a, single-crystal silicon wafer bearing a horizontally-disposed isolating silicon dioxide (SiO 2 ) layer, in turn ...